Semiconductor components are generally subjected to comprehensive functional tests after their fabrication. Only if these tests proceed successfully are the components shipped. The test contents relate to functionality with regard to the specification and a certain bias in numerous parametric directions, such as, for example, the voltage, the temperature and the operating frequency since the functionality of the semiconductor component is to be ensured even when the specifications are momentarily exceeded.
FIG. 1 shows an integrated semiconductor memory 100, which has a memory cell array 10 with memories cells SZ. The memory cells are generally connected in matrix form between word lines WL and bit lines BL. In the exemplary embodiment of FIG. 1, the memory cells SZ are connected to word lines WL1 and WL2 and to bit lines BL1, BL2, BL3. The memory cells are embodied as DRAM (Dynamic Random Access Memory) memory cells. An exemplary DRAM memory cell SZ13 is shown in FIG. 1 and includes a storage capacitor SC and a selection transistor AT. A control terminal of the selection transistor AT is connected to the word line WL1. In order to read from the memory cell or to write a data value to the memory cell, the selection transistor AT is controlled into the on state by a control signal on the word line WL1, so that the memory cell SZ is connected to the bit line BL3 in low-impedance fashion.
In addition to the memory cells SZ, the memory cell array of FIG. 1 also has redundant memory cells SZr that can be activated by a control signal on a redundant word line WLr for read and write accesses. In general, however, the redundant memory cells are accessed only when, in the event of a functional test of the integrated semiconductor memory, defective regular memory cells SZ have occurred that are then replaced by redundant memory cells SZr.
The function of the integrated semiconductor memory of FIG. 1 for a read or write access is explained below with reference to FIG. 2. FIG. 2 shows, in a first signal row, the profile of a clock signal CLK applied to a clock terminal T100 of the integrated semiconductor memory. The clock signal CLK is used to ensure that write and read operations are executed clock-synchronously with the clock signal CLK. Read, write, and other control operations are executed by driving a control terminal S100 of the integrated semiconductor memory with a command signal CMD. FIG. 2 shows the profile of the command signal CMD in the second signal row.
For a write access to a memory cell, for example, the memory cell SZ11 connected to the word line WL1 and the bit line BL1, an address signal AS is applied to an address terminal AD100 of the integrated semiconductor memory. The address signal is fed to an address register 50. If the control circuit 40 detects the command signal ACT at its control terminal S100, the control circuit 40 evaluates the address signal AS fed from the address register 50 and drives the word line WL1 with a control signal VPP via a word line driver 31 in a word line driver strip 30. The control signal VPP has a high level that switches the selection transistors AT of the memory cells SZ11, . . . , SZ1n connected to the word line WL1 into the on state. At the same time, the remaining word lines of the memory cell array 10, of which only the word line WL2 and the redundant word line WLr are illustrated in FIG. 1 for simplicity, are driven by a control signal VLL generated by the word line drivers 32 and 31r. The control signal VLL has a low level in comparison with the control signal VPP. The low level switches the selection transistors of the memory cells SZ21, . . . , SZ2n connected to the word line WL2 and the selection transistors of the redundant memory cells SZr connected to the redundant word line WLr into the off state.
Via the selection transistors AT of the memory cells SZ connected to the word line WL1 that are turned on, the storage capacitors SC of these memory cells are connected to the bit lines BL1, BL2 and BL3 in low-impedance fashion.
In order to write a data value to one of the memory cells of the word line WL1, a write command signal WR is applied to the control terminal S100. Based on the address signal AS, the control circuit 40 then selects one of the memory cells activated by the control signal VPP of the word line WL1 connected to a data input and output terminal DIO for writing an item of information. If an item of information is to be written to the memory cell SZ11 connected to the word line WL1 and the bit line BLI, a sense amplifier LV1 in a sense amplifier strip 20 connected to the bit line BL1 is activated. As a result of control terminal SLV1 being driven with a control signal CSL from the control circuit 40, the sense amplifier LV1, in the activated state, connects the bit line BL1 to a local data line LDQ. Further sense amplifiers LV2, LV3 connected to the bit lines BL2, BL3 are driven with a complementary control signal/CSL at their control terminals SLV2, SLV3 by the control circuit 40. The sense amplifiers LV2, LV3 are therefore controlled in high-impedance fashion, so that the bit lines BL2, BL3 connected to them are isolated from the local data line LDQ. The local data line LDQ is connected to a main data line MDQ via a controllable switch 60. The main data line MDQ is connected to the data input and output terminal DIO via an amplifier 70. A data signal present at the data input and output terminal DIO is amplified by the amplifier 70, fed via the controllable switch 60, the local data line LDQ, the sense amplifier LV1 controlled in low-impedance fashion, and the bit line BL1, and via the selection transistor controlled into the on state to the activated memory cell SZ11, and is stored therein. The selection transistors of the memory cells SZ11, . . . , SZ1n are turned off again after the end of the storage operation.
After a data retention time TR has elapsed, the data value written in the memory cell SZ11 is refreshed again since, despite the selection transistor of the memory cell SZ11 controlled in high-impedance fashion, leakage currents occur that lead to a slow flowing away of the charge stored on the storage capacitor SC of the memory cell SZ11. Such a refresh operation is carried out internally without the control circuit 40 being driven with an external command signal. The data contents of the memory cells connected to a common word line are refreshed during the refresh operation. In order to refresh the data contents of the memory cells SZ11, . . . , SZ1n, the selection transistors of these memory cells are controlled into the on state again by the control signal VPP on the word line WL1. The sense amplifiers LV1, . . . , LVn then again refresh the charge level stored in the memory cells SZ11, . . . , SZ1n with a full high or low charge level. The selection transistors are subsequently turned off again.
A read access to the memory cell SZ11 is described below with reference to FIGS. 1 and 2. The address register 50 is driven with the address of the memory cell SZ11 at the address terminal AD100. The control circuit 40 is again driven by the control signal ACT, and evaluates the address that is buffer-stored in the address register 50 based on the address signal AS. The control signal VPP is again applied to the word line WL1 connected to the memory cell SZ11, whereas the control signal VLL is applied to the remaining word lines. The selection transistors of the memory cells SZ11, . . . , SZ1n are thereupon switched into the on state, whereas the selection transistors of the memory cells SZ21, . . . , SZ2n of the word line WL2, for example, remain turned off. Depending on the charge level that was stored in the memory cells SZ11, . . . , SZ1n, a potential change, a signal swing occurs on the bit lines BL1, . . . , BLn. After a signal development time, the signal swing is developed with a sufficient level on the bit lines such that it can be detected by the sense amplifiers LV1 . . . , LVn and written back to the respective memory cells SZ11, . . . , SZ1n again after having been amplified. Thus, during the read-out operation, a simultaneous refresh operation of the memory cells connected to the word line WL1 activated by the control signal VPP takes place.
As a result of the control circuit 40 being driven with the external command signal RD, the sense amplifier is activated for assessing the potential state on the connected bit line. As a result of the activated sense amplifier LV1 being driven with the control signal CSL by the control circuit 40, the bit line BL1 is thereupon connected to the local data line LDQ in the sense amplifier LV1. The signal swing on the bit line BL1 amplified by the sense amplifier LV1 is fed via the local data line LDQ and the controllable switch 60 to the main data line MDQ, where the signal is amplified once again by the amplifier 70 and fed to the data input and output terminal DIO, at which it can be tapped off externally.
The remaining sense amplifiers LV2, . . . , LVn are driven by the complementary control signal/CSL, which each controls the sense amplifiers in high-impedance fashion. As a result, the bit lines BL2 and BL3 are isolated from the local data line LDQ.
As described above, by the control signal CSL, during the read-out of the memory cell SZ11, the bit line BL1 is connected in low-impedance fashion to the local data line LDQ via the sense amplifier LV1. In this case, the local data line LDQ represents a high capacitive load CL for the sense amplifier LV1. In some cases, this high capacitive load may entail incorrect writing back of the memory state of the memory cell to be read. The problem occurs, in particular, when the integrated semiconductor memory, after the command signal ACT, is driven by the command signal RD after a time period shorter than a critical delay time TRCD (Row Address to Column Address Delay).
In this case, the critical delay time TRCD is the time duration that lies between the external command signal ACT and the external command signal RD in order that the signal swing, the potential change, has developed on the bit line sufficiently in order that the sense amplifier can detect the small signal swing and can subsequently amplify it in one direction or the other, i.e., in the direction of a high voltage potential or in the direction of a low voltage potential.
Therefore, if a shorter time duration than the time duration of the critical delay time TRCD lies between the command signal ACT and the command signal RD, often the signal swing on the bit line has not yet developed sufficiently. The large capacitive load of the local data line LDQ then shifts the small potential change on the bit line, which is currently developing in one direction, in the opposite direction. The sense amplifier thus detects a signal swing which, for example, instead of lying above a threshold value, now lies below the threshold value. The threshold value may, for example, be the potential state on a complementary bit line likewise connected to the sense amplifier. Consequently, instead of a high charge level, a low charge level is now written back to the memory cell to be read. Instead of the data value originally stored in the memory cell, the complementary data value with respect thereto occurs at the data input and output terminal. In the case of a healthy bit line, the influencing by the capacitive load should not give rise to a polarization reversal above or below the threshold value, if the time duration of the critical delay time lies between the command signal ACT and the command signal RD. In case of a sick bit line, however, such a polarization reversal already occurs, in general, during the critical delay time.
A functional test of the integrated semiconductor memory involves testing whether the capacitive load of the local data line LDQ, during a read-out operation with the critical delay time TRCD, effects a rewriting of the data value to be read out by the sense amplifier.
FIG. 3 illustrates the individual test steps of the functional test in a signal flow diagram. At the beginning of the test, a first memory state H, corresponding to a memory state “1,” for example, is stored in the memory cells of the memory cell array 10. A second memory state L, for example, a memory state #0 is subsequently written to the memory cells connected to the word line WL1 allocated a word line address #0, and to memory cells connected to word lines with the word line addresses #4, #8, . . . The further word lines with the addresses #4, #8 are not illustrated for the sake of better clarity in the memory cell array 10.
For the duration of the data retention time TR, for example, for 64 ms, a disturbance signal is subsequently fed to adjacent word lines. In the example of FIG. 3, for the word line WL1 with the word line address #0, the associated disturbance signal is fed to the word line WL2 with the word line address #F, for the word line with the word line address #4 the disturbance signal is fed to the word line adjacent thereto with the word line address #3, and for the word line with the word line address #8 the disturbance signal is fed to the adjacent word line with the word line address #7. The disturbance signal on the adjacent word lines represents, for example, a fast change of the control signals VPP and VLL, which corresponds to a fast change between a high and low voltage potential on the adjacent word lines.
In order to examine the context of the functional test, for example, whether the memory state “0” in the memory cells of the word line WL1 has been disturbed by the high-frequency disturbance signal along the word line WL2, the individual memory cells SZ11, . . . , SZ1n connected to the word line WL1 are read and the memory state read out is compared with the value “0.” In this case, the read access is effected with the critical delay time TRCD. Firstly, a sense amplifier is activated, detects the instantaneous potential state on the bit lines connected to it, and starts to amplify the potential state in one direction or the other depending on whether it lies above or below the threshold value. During this amplification operation, the activated sense amplifier is driven by the control signal CSL. The bit line connected to the activated sense amplifier is thereby connected to the common data line LDQ. The memory content stressed by the disturbance signal of the memory cell to be read or the instantaneous potential state on the bit line connected to the relevant memory cell is thus also exposed to the capacitive load CL of the common data line LDQ. The capacitive load CL may effect, in particular on a sick bit line, as a further cause of error, a rewriting of the originally stored memory state to the memory cell to be read in that the instantaneous potential state on the bit line experiences a disturbance such that, instead of lying below the threshold value, for example, it now lies above the threshold value.
Since a read access to one of the memory cells, for example, to the memory cell SZ11, as described in the introduction, simultaneously results in an operation of refreshing the data content of the remaining memory cells SZ12, . . . , SZ1n likewise connected to the word line WL1, the entire test procedure, i.e., the preallocation of the first memory state “1” to the memory cells, the writing of the second memory state “0” to the memory cells SZ11, . . . , SZ1n to be tested, the driving of an adjacent word line WL2 with a disturbance signal during the data retention time TR, and the concluding read-out of only a single memory cell, has to be repeated for each memory cells SZ11, . . . , SZ1n connected to the word line WL1. Only when all memory cells SZ11, . . . , SZ1n from the bit line BL1 with a bit line address ystart through to the bit line BLn with a bit line address yend have been read is the functional test ended.
Since the time duration during which the disturbance signal is fed in on the adjacent word line WL2, i.e., the data retention time TR, represents the significant test time factor of a test time TTest, the functional test described requires, for a memory cell array having n memory cells to be tested, in total a test time TTest≈n*TR. Consequently, for 1024 memory cells to be tested along a word line, the result is a total test time TTest of approximately 65 s.
A method for testing an integrated semiconductor memory that reduces the required test time, and applicable, in particular, to functional tests of an integrated semiconductor memory to test whether the memory content of memory cells connected to a word line is influenced by a disturbance signal on an adjacent word line, is desirable. An integrated semiconductor memory in which the required test time for carrying out a functional test in which the memory content of memory cells connected to a word line is influenced by a disturbance signal on an adjacent word line is reduced is also desirable.